Non-volatile semiconductor memory devices have a beneficial characteristic in that previous data are not erased although power is not supplied. Non-volatile memory devices are widely used in mobile telecommunication systems and computer memory cards.
Generally, non-volatile memory devices include a stacked gate structure. The stacked gate structure includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer and a control gate electrode, which are sequentially stacked on a channel region of the cell transistor. Thus, the non-volatile memory device with the stacked gate structure has a high step difference between a cell array region and a peripheral circuit region. This can lead to difficulty in subsequent processing of the memory device. Additionally, a process of patterning the floating gate is complicated and it is not easy to increase a surface area of the floating gate. The surface area of the floating gate influences a coupling ratio of the cell transistor, and the coupling ratio relates to a program characteristic and an erase characteristic of the cell transistor. In other words, it is required to increase the surface area of the floating gate in order to improve the program characteristic and the erase characteristic. However, with a highly integrated non-volatile memory device, there are limitations in increasing the surface area of the floating gate.
FIG. 1 illustrates a cross-sectional view explaining a conventional SONOS cell transistor.
Referring to FIG. 1, a source region 3s and a drain region 3d, which are spaced from each other, are arranged in a semiconductor substrate 1. A tunnel oxide layer 5, a charge trapping layer 7, a blocking oxide layer 9 and a gate electrode 11 are sequentially stacked on a channel region between the source region 3s and the drain region 3d. The tunnel oxide layer 5 is formed of a thermal oxide layer that is thinner than 20 Å, and the charge trapping layer 7 is formed of silicon nitride layer. Additionally, the blocking oxide layer 9 is formed of a CVD oxide layer with a thickness of about 60 Å, and the gate electrode 11 is formed of a conductive layer such as a doped polysilicon layer.
FIG. 2 illustrates a graph explaining an erasing operation of a conventional SONOS cell transistor. In FIG. 2, a horizontal axis indicates an electric field E applied to the tunnel oxide layer 5 or the blocking oxide layer 9 of FIG. 1, and a vertical axis indicates a tunneling current Itun flowing through the tunnel oxide layer 5 or the blocking oxide layer 9 according to the electric field E.
Referring to FIG. 2, the tunneling current Itun flowing through the blocking oxide layer 9 having a thickness of about 60 Å is subject to the Fowler-Nordheim (F-N) tunneling, and is proportional to the electric field E applied to the blocking oxide layer 9 (Refer to a curve ({circle around (1)}). However, a tunneling current Itun flowing through the tunneling oxide layer 5 shows a remarkably low increment in comparison with the tunneling current Itun flowing through the blocking oxide layer 9 (Refer to curves {circle around (2)} and {circle around (3)}). The curve {circle around (2)} indicates a tunneling current flowing through a thin tunnel oxide layer having a thickness of about 20 Å, and the curve {circle around (3)} indicates a tunneling current flowing through a tunnel oxide layer having a thickness of about 30 Å. Consequently, the tunneling current flowing through the tunnel oxide layer 5 having a thickness of 20 Å to 30 Å is subject to a direct tunneling, differently from the F-N tunneling current flowing through the blocking oxide layer 9. The dominant tunneling mechanism is determined by the thickness of the tunnel oxide layer or the blocking oxide layer.
As can be seen from the curves {circle around (2)} and {circle around (3)}, as the thickness of the tunnel oxide layer 5 is increased, the tunneling current is further decreased. Consequently, in the case that the tunnel oxide layer 5 is thicker than 20 Å, the erasing operation may be unsuccessfully performed. This is because the tunneling current flowing through the blocking oxide layer 9 is larger than other tunneling current flowing through the tunnel oxide layer 5 at an electric field region (a lower region than Ec) where at least a tunneling current may flow, as shown in FIG. 2. That is, since the number of electrons injected into the charge trapping layer 7 through the blocking oxide layer 9 is greater than that of holes injected thereinto through the tunnel oxide layer 5, it is difficult to effectively accomplish the erasing operation of removing electrons trapped in the electron trapping layer 7.
Thus, for a successful erasing operation, the tunnel oxide layer 5 should be thinner than 20 Å. However, in the case that the tunnel oxide layer 5 is thinner than 20 Å, it is difficult to improve a data retention characteristic, i.e., a bake retention characteristic performed at a temperature of 85° C.